Today, as the integrated circuit has become the core of all electronic products, simply being able to design an integrated circuit is not enough, but the main challenges lie in optimizing the high performance and low consumption design, in robustness with tolerance to PVT variation and improvement in yield. I know that these mysteries can only be unlocked through design innovation, the development of new ideas and algorithms to increase the performance of EDA tools. I believe ICS Research Group @ University of Texas, Austin is an ideal choice that can help me evolve my ideas to work on these challenges and overcome them, through a well-structured curriculum, excellent faculties and research facilities. My curiosity towards applied sciences began to grow since high school. During my engineering studies; I found the courses on digital design extremely fascinating; I devoted a lot of time to labs and libraries and this addiction motivated me to take it up as a specialization. Through intensive screening, I took the opportunity of a research internship at STMicroelectronics Inc to complete my master's thesis in this area. The bird's-eye view of FPGA design, exposure to challenges in SoC design, and direct interaction with designers further stimulated my growing interest in IC design as a career. My hard work finally paid off when I was awarded the best thesis award in the department along with a placement offer from STMicroelectronics. A stronghold in digital design and VLSI along with extensive practical exposure internship got me job offers from various chip design companies such as Freescale Semiconductor, Texas Instruments, Cypress Semiconductor and STMicroelectronics. Outside of my curriculum, I worked on "Digital Image Processing", while assisting Dr. Kulbir Singh, in one of his research projects at Thapar Center for Industrial Research and Development in my 8th semester of B. Engg. Carefully considering my area of ​​interest and offered job profiles from various semiconductor companies, I decided to join Freescale Semiconductor Inc as IC Design Engineer in Place & Route domain. Today, as a senior IC R&D engineer, I am involved in research and design activities in the complete SoC physical design flow from RTL to GDSII such as logic synthesis, placement and routing, and static timing analysis. My area of ​​expertise includes “OCV Aware Design Optimization, Leakage and Dynamic Power Reduction, Design Automation and Robust Clock Tree Design for Security Clusters and Automotive ICs.” My connection with Freescale strengthened the essential foundations laid during my undergraduate studies. Freescale's creative atmosphere led me to innovate several new methodologies and implementations, which I submitted for review to Freescale's Patent Review Board.